1. Field of the Invention
The present invention relates generally to integrated circuit structures, and more specifically to an electrostatic discharge protection circuit and layout structure suitable for use with CMOS devices.
2. Description of the Prior Art
Integrated circuit devices, especially CMOS devices, are susceptible to electrostatic discharge (ESD) induced failure. ESD is typically a high voltage, short duration spike such as caused by discharge of a built up static charge. ESD can damage or completely destroy integrated circuit devices if provisions are not made to minimize its effects.
ESD protection circuits are employed on all input and output pins of most integrated circuit devices. ESD protection circuits currently in wide use typically employ diode clamps, lateral punch-through devices, and guard ring collectors around an input/output bonding pad. These circuits are reasonably effective at protecting input circuits, but are less effective at protecting output circuits from very high voltage transients over approximately 3,000 volts.
The output circuitry of CMOS devices is especially vulnerable to ESD induced failure because the drain of an N-channel drive transistor is tied directly to the output bonding pad of the device. For high ESD voltages, the N-channel output device will be driven into snapback breakdown, which either permanently destroys the drain junction or ruptures the gate oxide of the transistor. In either case, the integrated circuit is rendered wholly or partially non-functional.
As the packing density for CMOS devices continues to increase, they will only become more susceptible to ESD induced failures. The use of thinner gate oxides, shallower source/drain junctions, and more closely spaced components simply exacerbates the problems which have been experienced in the past.
It would be desirable to provide an ESD protection circuit and structure which is suitable for use with CMOS devices, and which provides improved ESD protection. It would be further desirable for such a circuit and structure to be compatible with standard CMOS processing, and provide enhanced protection with little or no additional process flow complexity.